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The 32/7780 32/7705, 32/7750 is the first simultaneously on the same system, a benefit that, until now, only the owners of multi-million dollar main-frames could obtain.
The higher system throughput made possible by multiple stream processing meets or exceeds the rigorous performance requirements demanded by high-end engineering, real-time, and scientific users.
The 32/7780 is a CPU/IPU combination. The CPU is the same powerful CPU used in the 32/77 computer. The 111-I is an Internal Processing Unit. Its function is purely computational. The IPU and CPU have equal computational abilities, but the CPU retains control of I/O and interrupt operation. The high system throughput that results from this combination makes the 32/7780 a powerful balanced system.
Both the CPU and the IPU can have their own High-Speed Floating-Point Unit. The Floating-Point Units provide the CPU and IPU with the ability to perform floating-point operations with very large operands in a fraction of the time required by standard firmware floating-point implementations.
Scientific Accelerators are added to both the CPU and IPU. A Scientific Accelerator puts Scientific Runtime Library subroutines in Writable Control Storage boards, connected to the CPU and IPU. Assembly Language or FORTRAN users experience much faster execution of programs, since a firmware implementation runs much faster than equivalent assembly Language programs.
In a multi-task environment of any type, the SYSTEMS 32/7780 computer proves superior to traditional architectures.
The 32/7780 includes the following features:
600 ns MOS Memory with ECC
2 or 4 Way Memory Interleaving
Direct Memory Addressing of Bit, Byte, Halfword, Word, or Doubleword Operands
Multilevel Indirect Addressing
Eight 32-bit General Purpose Registers
Regional Processing Units
Up to 112 Priority Interrupt Levels for I/O, External Interrupts, and Traps
MPX-32 Operating System
Field-Proven Utility and Applications Programs
Modular Construction for Configuration flexibility
Advantages provided to the user by the 32/7708 come in the form of higher system throughput in both single process and multiprocess applications.
A traditional computer with a throughput of "X" is show in Figure 1A. Increasing he speed of that processor will lead to higher system throughput, but he advantages are small and expensive since the increase in throughput is inherently additive.
Figure 1B shows the 32/7780 approach. A multiple stream computer can significantly enhance the system throughput without restoring to expensive high-speed implementations.
This multiplicative throughput enhancement offers a tangible improvement over conventional approaches to the problem.
The improvement is immediate. The users throughput increases without any reprogramming. By taking advantage of multiprocess programming, The user can fully realize the potential of the architecture by segmenting his program into compute and I/O tasks, and further improve throughput.
The 32/7780 computer can also be seen as a "gracefully degrading system" in the event of a processor failure. If the CPU fails, the user can simply jumper the IPU turning it into a CPU, and start running again. If the IPU fails, the CPU can keep running without user intervention. Spares requirements and system downtime are reduced significantly.
The 32/7780 is a true Multiple Stream Processor. Two tasks can simultaneously run on the CPU and the IPU. Both the CPU and IPU have identical computational capabilities while the CPU handles all I/O and interrupts.
This balanced architecture allows the programmer to segment applications, and specify which tasks are to be given to the CPU or IPU. Instructions not allowed in the IPU will quickly passed to the CPU for execution.
Although the IPU is transparent to most users, some multitasking applications can be affected by the concurrent execution of individual tasks. For example, two tasks which access a shared database may need to use MPX-32 synchronization primitives (e.g.. Resource Marks), to avoid inconsistencies in the database. Although the bit manipulation instructions. ABM, SBM, ZBM do provide automatic synchronization between IPU and CPU, the Add Register to memory instruction. ARMX does not. Tasks may also specify that they need to run in the CPU for all or part of their execution.
The 32/7780 is a high-performance 32-bit computing system built around multiple high-speed, synchronous, shred, multiplexed buses: The SelBUS and one or more memory buses (Figure 2). The SelBUS provides the path for communication between all functional elements of the system. It runs vertically through the logic chassis and distributes information at a rate of 26.67 million bytes per second. The modules that plug into the SelBUS include: the CPU and IPU, High-Speed Floating-Point Units, Real-Time Option Modules (RTOM), Input/Output Microprogrammable Processors (IOM) and Regional Processing Units (RPU), which are used as I/O controllers. The Writable Storage Options also occupy SelBUS slots but are electrically connected directly to the CPU.
The Memory Bus Controllers (MBA) plug into the SelBUS and control up to 4 Megabytes of memory on the Memory Bus. The Memory Bus is a separate Memory chassis.
The SelBUS is a high-speed, synchronous, time division multiplexed bus that can transfer data at the rate of 26.67 million bytes per second. Interrupt and SelBUS priority are uniquely definded and are not module-position dependent. Each module is assigned 1 of the 23 SelBUS priority lines by simple jumper settings.
The SelBUS is a bi-directional bus. Thirty-two data lines and 24 address lines on the SelBUS are used to send and receive data between system components. These transfers can occur every 150 nanoseconds. The address lines are used to select the desired subsystem component or memory location for a data transfer operation. Both data and address lines operate simultaneously.
The CPU and IPU are each implemented on three plug in boards. Two of these boards make up the Arithmetic Logic Unit. The third board is the control unit, which contains the firmware implementing the instruction set and control logic.
The 32/7780 computers use instruction lookahead for task instruction execution. Instruction fetches are made concurrently with instruction execution and with decoding a previously fetched instruction. The functional difference between the CPU and IPU are shown in Table 1.
Both 32/7780 CPU and IPU have a set of eight high-speed, general purpose registers for use by the programmer for arithmetic, logical, and shift operations. Three general purpose registers R1, R2, and R3 - can also he used for indexing operations. Register RO can also be used as a link register, Register R4 can be used as a mask register.
The instruction repertoire in the 32/7780 computer includes 187 standard instructions.
The functional classifications and the number of instructions each class are as follows:
The eight bit-manipulation instructions provide the capability to test and set, test and zero, add to, or simply, test any selected bit in any memory location within 512KB of memory or in any general purpose register.
Instructions are either halfword instruction (16 bits) or word instruction s (32) bits. The word instructions primarily reference memory locations, while the halfword instructions deal primarily with register operands.
Because approximately one-third of the instructions are halfword instructions, program memory space is conserved by packing tow consecutive halfword instructions into a single memory location. The two instructions are fetched simultaneously. Fewer memory accesses make programs execute faster.
Hardware Memory Management
The 32/7780 computer operates under the MPX-32 Operating System. MPX-32 is a mapped executive, and has two ways to address memory:
Mapped, Nonextended addressing allows the CPU and IPU to address any instruction or operand (bit, byte, halfword, word, or doubleword) within a tasks logical address space. This space consists of 512 KB of logical memory dispersed anywhere within the 16 MB physical memory.
MPX-32 allows multiple logical address spaces. A user can access
instructions and operands within the logical address space in which his
task resides. Physical blocks of memory can be common to many logical
address spaces; thus, tasks in different logical address spaces can
share common blocks of physical memory.
Mapped, Extended addressing provides all the capabilities of Mapped, Nonextended addressing plus access to a extended logical address space. This space consists of 512 KB of memory beyond the primary logical address space. It allows the user additional memory space to store data (operands). Each extended logical address space can be 512 KB long, dispersed anywhere within 16 megabytes of physical memory. The combination of primary and extended logical address space supports programs up to one megabyte long. The executable code must lie within the primary logical address space but operands can be in either the primary logical or extended logical address space.
The 32/7780 hardware supports two other addressing methods. These are provided for compatibility with earlier machines and are not supported by MPX-32. They are:
All 32/7780 Computers include a Memory chassis, a Memory Bus, Refresh Board, Memory Bus Controller (MBC), and Memory Modules.
The Memory chassis provides slots for up to 16 MOS Memory Modules; therefore, the inherent memory expansion capability of the 32/7780 computer 4 MB. Expansion to 16 million bytes is accomplished by adding Memory Support Packages. Each Memory Support package provides an additional chassis, MBC and power and can support up to 4 MB.
The Memory Modules used in the 32/7780 provide 256K bytes of 600 ns MOS memory with ECC. The MOS Memory is organized in 39-bit words: 32 bits of data and seven Error Correction Code Bits (ECC). During write operations, the ECC bits are generated and stored in memory. When a read memory operation takes place, the ECC bits are checked. If a 1-bit error is detected, the error is corrected. If two bits are in error, an error signal is generated.
The MBC in the 32/7780 Computer provides an interface between the SelBUS and the Memory bus. It can overlap and interleave up to four memory operations, and can handle one memory request during each 150-nanosecond cycle.
When a system has two memory modules (or any number divisible by
two), memory can be two-way interleaved to provide increased throughput.
Likewise, with four memory modules, memory can he four-way interleaved.
The Memory Protect system provides write protection for individual units of memory, called protection granules. A protection granule consists of 512 words. Up to 256 pages (128K words) can be protected at a time. The memory protect registers can be changed by executing privileged instructions. In addition, memory management provides memory protection for each 32 KB memory block or logical address space. One protect bit is associated with each 32 KB memory block.
The power and flexibility of the 32/7 780 Computers I/O system is derived from three sources: intelligent lnput/Output Microprogrammable Processors (IOM), High-Speed Data interface (HSD). and Regional Processing Units (RPU). All provide high-speed block-oriented transfers direct to memory.
The MPX-32 operating system supports 16-Megabyte addressing, command chaining, and data chaining via extended protocols, to provide a powerful I/O system. Modem support under MPX-32 adds to the scope of the 1/0 system, providing communications processing capabilities.
The High-Speed Data interface (HSD) is capable of transferring data at 3.2 megabytes per second. The Regional Processing Unit (RPU) includes 2048 32-bit words of PROM and, optionally, 4096 32-bit words of RAM for user programmable firmware or data. Special interfaces can be implemented on the RPU by providing firmware and designing the device interface, which for the most part consists of matching signal levels between the RPUs
Microprogrammable Processor and the device.
The 32/7780 Computer has a total of 12 I/O instructions. Upon execution of a single instruction, an I/O Controller can be conditioned to transfer one or more blocks of data between the external device and memory. Once the transfer is initialized, the controller takes charge of the I/O operation, and the CPU is free to perform other tasks. When the transfer is completed, an I/O Controller can notify the CPU by an interrupt.